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本帖最后由 職業(yè)法師劉海柱 于 2020-4-8 10:11 編輯
刷了錯誤的包,現(xiàn)在接TTL啟動死循環(huán)。盒子型號E900V21C
GXLX:BL1:9ac50e:4a8da0;FEAT:ADFC318C:0;POC:3;RCY:0;EMMC:0;READ:0;0.0;CHK:0;
TE: 190948
BL2 Built : 14:55:32, Mar 24 2017.
gxl g4bbe26f - shuiyuan.huang@droid10-sz
Board ID = 1, adc=79
set vcck to 1070 mv
set vddee to 1070 mv
CPU clk: 1200MHz
Can't match board id, use default ddr_set[0]
DQS-corr enabled
DDR scramble enabled
DDR3 chl: Rank0+1 @ 792MHz - FAIL
DDR3 chl: Rank0 @ 792MHz - PASS
GXLX:BL1:9ac50e:4a8da0;FEAT:ADFC318C:0;POC:3;RCY:0;EMMC:0;READ:0;0.0;CHK:0;
TE: 195699
BL2 Built : 14:55:32, Mar 24 2017.
gxl g4bbe26f - shuiyuan.huang@droid10-sz
Board ID = 1, adc=79
set vcck to 1070 mv
set vddee to 1070 mv
CPU clk: 1200MHz
Can't match board id, use default ddr_set[0]
DQS-corr enabled
DDR scramble enabled
Pull down ddr cke
DDR3 chl: Rank0+1 @ 792MHz - FAIL
DDR3 chl: Rank0 @ 792MHz - PASS
GXLX:BL1:9ac50e:4a8da0;FEAT:ADFC318C:0;POC:3;RCY:0;EMMC:0;READ:0;0.0;CHK:0;
TE: 196392
BL2 Built : 14:55:32, Mar 24 2017.
gxl g4bbe26f - shuiyuan.huang@droid10-sz
Board ID = 1, adc=79
set vcck to 1070 mv
set vddee to 1070 mv
CPU clk: 1200MHz
Can't match board id, use default ddr_set[0]
DQS-corr enabled
DDR scramble enabled
Pull down ddr cke
DDR3 chl: Rank0+1 @ 792MHz - FAIL
DDR3 chl: Rank0 @ 792MHz - PASS
GXLX:BL1:9ac50e:4a8da0;FEAT:ADFC318C:0;POC:3;RCY:0;EMMC:0;READ:0;0.0;CHK:0;
TE: 195611
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